Simulating the VHDL generated from Arx is straightforward. As opposed
to the generated C++, the hierarchy of the Arx source code
is preserved in the VHDL. For source code in the file foo.arx
, the
VHDL file foo.vhd
is generated. Top model top
in Arx becomes entity
foo
in VHDL. Around this model a wrapper model is generated
with entity name foo_std
. This wrapper model converts all inputs
and outputs to VHDL data type std_logic
or std_logic_vector
for easy interfacing with other design tools.